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PLC-5/12 6K 1 resident none 128 (8-pt) 1, 256 2 Maximum I/O possible using 16-pt modules with 2-slot addressing or 32-pt modules with 1-slot addressing. Modules Addressing Reference 1785 PLC-5 2 The memory map in Figure 1 shows the logical arrangement of the data table area of memory in a 1785 PLC-5 processor. This map does not represent the physical structure of the memory, but it provides the addressing scheme for the memory in the 1785 PLC-5 data table. The The PLC-5 and SLC-500 use a rack/slot/register/bit method for addressing the I/O modules. For example input point 15 in slot 2 of rack 1 would be addressed - I:1:2/15. The same goes for outputs. Now the legacy problems prop up. In the old days most things were octal so AB allows for different methods for addressing modules in the rack.

Micro/SLC-500/PLC 5 Addressing Formats. The general format of value names for data from the listed controllers matches the naming convention used by the programming software. The format is shown below. The parts of the name shown in in square brackets [] are optional.

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